Open lkolbly opened 2 years ago
Xilinx (and probably iverilog) issue warnings if a variable is used before it's declared.
It doesn't appear to be a functional issue, but best to not have such warnings.
Actually, as an extension, we should probably put all module instantiations before they're used also.
Agreed
Xilinx (and probably iverilog) issue warnings if a variable is used before it's declared.
It doesn't appear to be a functional issue, but best to not have such warnings.