What good are writing modules, if you can't use them?
I think there are multiple syntaxes we will ultimately have for instantiating modules. As a basic start, I think we can do something like this:
instantiate module_name as instance_name;
instance_name.some_input[t] = x[t-1];
x[t] = instance_name.some_output[t];
As a contrived example:
module add(bits<32> a, bits<32> b) -> (bits<32> c) {
c[t] = a[t-1] + b[t-1];
}
module add3(bits<16> tag_in, bits<32> a, bits<32> b, bits<32> c) -> (bits<16> tag_out, bits<32> c) {
instantiate add as add1;
instantiate add as add2;
add1.a[t] = a[t];
add1.b[t] = b[t];
add2.a[t] = add1.c[t];
add2.b[t] = c[t-2];
c[t] = add2.c[t];
tag_out[t] = tag_in[t-2];
}
There is no additional registering as part of a module's inputs or outputs (as highlighted by the tag in the code example above, which should follow the mathematical operation).
This syntax allows a couple nice things, namely:
Allowing instantiating the same module multiple times.
Allowing in the future specifying module-level generic parameters (types, numbers, etc.) for different instantiations.
The generated code should instantiate a module in the generated Verilog (as opposed to inlining the module in Ripstop, and then generating inlined code).
This has the implication that we could instantiate Verilog modules this way, which implies that maybe we could instantiate a module that doesn't exist (under the assumption that it will be supplied by Verilog). However, we should not assume this - if the compiler can't positively identify a definition for the module, it should error. (we'll come up with a syntax for declaring external modules)
If not all of the inputs to a module instance are specified, an error should be thrown. Outputs can be ignored though.
What good are writing modules, if you can't use them?
I think there are multiple syntaxes we will ultimately have for instantiating modules. As a basic start, I think we can do something like this:
As a contrived example:
There is no additional registering as part of a module's inputs or outputs (as highlighted by the tag in the code example above, which should follow the mathematical operation).
This syntax allows a couple nice things, namely:
The generated code should instantiate a module in the generated Verilog (as opposed to inlining the module in Ripstop, and then generating inlined code).
This has the implication that we could instantiate Verilog modules this way, which implies that maybe we could instantiate a module that doesn't exist (under the assumption that it will be supplied by Verilog). However, we should not assume this - if the compiler can't positively identify a definition for the module, it should error. (we'll come up with a syntax for declaring external modules)
If not all of the inputs to a module instance are specified, an error should be thrown. Outputs can be ignored though.