[FIRRTL] Need an intermodule dead code elimination pass

[drom]

The following FIRRTL program

circuit top_mod :
  module mod_0 :
    input inp_a: UInt<1>
    output tmp18: UInt<1>
    tmp18 <= inp_a
  module top_mod :
    input a: UInt<1>
    inst U0 of mod_0
    U0 is invalid
    U0.inp_a <= a

Compiled with firtool a_top_mod.fir --lower-to-hw --expand-whens --infer-widths --lowering-options=noAlwaysFF --verilog -o=a_top_mod_new.v produces this Verilog:

module mod_0(
  input  inp_a,
  output tmp18);

  assign tmp18 = inp_a; // a_top_mod.fir:2:3
endmodule

module top_mod(
  input a);

  wire U0_tmp18;    // a_top_mod.fir:8:5

  mod_0 U0 (    // a_top_mod.fir:8:5
    .inp_a (a),
    .tmp18 (U0_tmp18)
  );
endmodule

Compiled with firrtl-1.5-SNAPSHOT produces this Verilog:

module top_mod(
  input   a
);
endmodule

Module mod0 and U0 instantiation should be removed from the output because nothing depends it's outputs.

[uenoku]

It's already handled by IMDCE pass.

// Generated by CIRCT firtool-1.37.0
module top_mod(
  input a
);

endmodule