[FIRRTL] Handle Illegal Aggregate Connects in Parser (or LowerTypes?)

[seldridge]

Currently, we will convert illegal ground connects to partial connects where the RHS is larger than the LHS. However, if a user passes in an aggregate with this property, we need to emit element-wise partial connects. (Emitting an aggregate partial connect will change connection semantics.) Currently LowerTypes will create an illegal connect when it needs to pad.

Consider:

circuit Foo:
  module Foo:
    input a: {a: UInt<2>}
    output b: {a: UInt<1>}

    b <= a

This produces:

# firtool Foo.fir                    
Foo.fir:6:7: error: destination width 1 is not greater than or equal to source width 2
    b <= a
      ^
Foo.fir:6:7: note: see current operation: "firrtl.connect"(%arg1, %arg0) : (!firrtl.uint<1>, !firrtl.uint<2>) -> ()

[seldridge]

This is fixed on main. This is now parsed into subfield and strictconnect operations. Final Verilog output matches the SFC with:

module Foo(
  input  [1:0] a_a,
  output       b_a);

  assign b_a = a_a[0];
endmodule