[FIRRTL] Vector/Bundle create operation?

[uenoku]

Consider the following fir.

circuit Test :
   module Test :
     input clock: Clock
     input a1 : UInt<1>
     input a2 : UInt<1>
     input a3 : UInt<1>
     input a4 : UInt<1>
     reg c :  UInt<1>[2][2], clock
     c[0][0] <= a1
     c[0][1] <= a2
     c[1][0] <= a3
     c[1][1] <= a4

With MergeConnectionsPass introduced by https://github.com/llvm/circt/pull/2459, we will get something like:

   automatic logic [1:0][1:0] _T = {a4, a3, a2, a1}; 
    c <= _T;

This is because currently FIRRTL dialect doesn't have operations to create vector/bundle from elements. From that reason　https://github.com/llvm/circt/pull/2459 uses concat+bitcast to create aggregate values. As a result, it loses information about structures. If there are firrtl.vector_create or firrtl.bundle_create, we should be able to emit something like:

   automatic logic [1:0][1:0] _T = {{a4, a3}, {a2, a1}}; 
    c <= _T;

[uenoku]

Dup of https://github.com/llvm/circt/issues/1352