[FIRRTL][Verilog] Use Xcelium Coverage Exclusion Magic in Addition to VCS

[seldridge]

Currently we only emit extracted covers with the VCS magic file-level comment to exclude them:

// VCS coverage exclude file 
...

However, anywhere we emit this, we should also emit the Xcelium magic off/on comments. Xcelium looks like:

// pragma coverage block = off, toggle = off
...
// pragma coverage block = on, toggle = on

I am not super stoked about this option (and also note that the Xcelium pragmas I've been given are turning off specific types of coverage which may not be the case for all users 🥲 ) and would like to have a better mechanism to indicate that something is a cover, what file it should go to, and what simulators you are using so that we aren't just dropping verbatim Verilog comments all over the place.

[darthscsi]

We need an encoding for the behavior and lowering/emission options for different (possibly multiple) tools.

[uenoku]

would like to have a better mechanism to indicate that something is a cover, what file it should go to

+1 on this. I'm wondering if we can create coverage_exclude_file.f so that we can exclude those files directly from tools instead of relying on pragmas. Implementation wise, I think we can add "coverage_exclude_module" attribute to modules we want to exclude and gather them in ExportVerilog.

[srivatsa611y]

FYI about the comments and pragmas being added. The vcs comment, makes sure we collect only assert coverage, or coverage on the cover properties written in the file and ignore the line, branch and toggle coverage in those files.

We got the comments equivalent in xcellium which does the same. But the code has to be wrapped in the pragma comments.