[FIRRTL][GrandCentral] ReferenceDataTapKey causes errors on unknown widths when it should not

[jackkoenig]

Bug is present on both head of main and CIRCT sifive/1/20/0.

Consider:

circuit Top : %[[
  {
    "class": "sifive.enterprise.grandcentral.DataTapsAnnotation",
    "keys": [
      {
        "class":"sifive.enterprise.grandcentral.ReferenceDataTapKey",
        "source":"~Top|Foo>sum",
        "sink": "~Top|Top>tap"
      }
    ]
  }
]]
  module Foo :
    input in : UInt<8>
    output out : UInt<8>

    ; UInt(1) should not need a width
    node sum = tail(add(in, UInt(1)), 1)

    out <= sum

  module Top:
    input in : UInt<8>
    output out : UInt<8>

    inst foo of Foo
    foo.in <= in

    wire tap : UInt<8>

    out <= tail(add(foo.out, tap), 1)

Running firtool on this gives the error:

datatap-width-bug.fir:25:10: error: 'firrtl.asUInt' op inferred type(s) '!firrtl.uint' are incompatible with return type(s) of operation '!firrtl.uint<8>'
  module Top:
         ^

It's complaining about UInt(1). If you add a width to that UInt, or if you get rid of the DataTapsAnnotation, the error goes away.

[jackkoenig]

The example above is a bit trivial, but it can manifest with any unknown width which would otherwise be legal, eg.

    wire w : UInt
    w <= add(in, UInt<1>(1))
    node sum = tail(w, 1)

This gives the same problem