Closed seldridge closed 1 year ago
Some observations after thinking about this:
sv.system.sampled
op is coming from an assertion that gets extracted.sv.system.sampled
op does not have the trait Pure
which will block it from getting CSE'd or removed meaning that it hangs around after SVExtractTestCode
runs. (It probably should have this?)PrepareForEmission
still needs to do the right thing here, even if sv.system.sampled
isn't removed, i.e., when optimizations are disenabled. Currently, prepare is removing the sv.system.sampled
op as it is inlinable and has no uses. The icmp
is then left in a situation where prepare should have created a wire for it, but no such wire was created. ExportVerilog
then asserts.Thanks for a small reproducer! That's exactly what I was thinking of: https://github.com/llvm/circt/pull/4487, https://github.com/llvm/circt/pull/4486
I agree that sampled needs to be pure, and isExpressionEmittedInline
should return true for dead expressions.
I stumbled across the following assertion failure due to prepare for emission not generating a wire for an
icmp
operation.Consider:
Compiling this with
circt-opt Tmp.mlir -export-verilog
produces a nice crash: