Open seldridge opened 1 year ago
Oh no! FWIW before PrettyPrinter port, this produced the following (wrong) input, either way this should be fixed!
circuit Foo :
module Foo :
input clock : Clock
input a : UInt<1>
output b : UInt<1>
wire : UInt<1> @[./issue-5204.mlir 4:10]
reg r : UInt<1>, clock with :
reset => (UInt<1>(1), ) @[./issue-5204.mlir 5:10]
<= r @[./issue-5204.mlir 6:5]
(from circt-translate
1.39.0g20230420_640e43b
)
Looks like the wire is wrong too, and inspecting the emitter it seems to expect operations to already have names (and does this sort of problematic thing if they don't).
This variant of the original input works, for example (%0
-> %w
):
firrtl.circuit "Foo" {
firrtl.module @Foo(in %clock: !firrtl.clock, in %a: !firrtl.uint<1>, out %b: !firrtl.uint<1>) {
%c1_ui1 = firrtl.constant 1 : !firrtl.uint<1>
%w = firrtl.wire : !firrtl.uint<1>
%r = firrtl.regreset interesting_name %clock, %c1_ui1, %w : !firrtl.clock, !firrtl.uint<1>, !firrtl.uint<1>, !firrtl.uint<1>
firrtl.strictconnect %w, %r : !firrtl.uint<1>
}
}
Maybe should add names before running emitter or teach it to generate names if none are present?
Consider the following FIRRTL Dialect:
This produces a nice crash in the exporter (
circt-translate -export-firrtl Bar.mlir
):