[FIRRTL] Useless wire names could be useful as debug information

[uenoku]

https://github.com/llvm/circt/pull/5288 changed DropName pass to literally drop useless names (mostly created as Chisel temporaries) by default for better verilog output but these names were previously used for error messages. For example, ExpandWhen is not able to produce good messages for wires created as Chisel temporary.

circuit Foo :
  module Foo :
    wire _foo_WIRE: UInt<1> @[foo.scala 0:0]

$ firtool foo.fir
foo.scala:0:0: error: sink "" not fully initialized in module "Foo"

[darthscsi]

Isn't --preserved-values=named what we are using? In this case it looks good.

[dtzSiFive]

Issue maybe should be filed re:producing better diagnostics when names aren't found/present, specifically in ExpandWhen's but would be good to look around for where else this might be prone to producing things like "".