[FIRRTL] PlusArgs Intrinsics lower to SystemVerilog with high impedance values

h/t @chick for finding the issue, @seldridge for minimizing it, and @uenoku and @darthscsi for identifying the problem

Consider the following FIRRTL

FIRRTL version 3.0.0
circuit Foo :
  module Foo :
    input clock : Clock
    output x : UInt<1>
    inst bar of Bar
    wire baz : UInt<1>
    connect baz, bar.found
    connect x, baz
  intmodule Bar :
    output found : UInt<1>
    output result : UInt<32>
    intrinsic = circt_plusargs_value
    parameter FORMAT = "herp"

With relatively recent firtool, you get:

// Generated by CIRCT firtool-1.48.0-106-ga840c9397
module Foo(
  input  clock,
  output x
);

  assign x = 1'bz;
endmodule

llvm / circt

[FIRRTL] PlusArgs Intrinsics lower to SystemVerilog with high impedance values #5722