[FIRRTL] Uninitialized input port error for Integer input, IMDCE bug

[dtzSiFive]

Simple class with input driven by an integer:

FIRRTL version 3.2.0
circuit InputProp:
  class Test :
    input in : Integer

  module InputProp:
    object o of Test
    propassign o.in, Integer(5)

MLIR before lower-classes:

module {
  firrtl.circuit "InputProp" {
    firrtl.class private @Test(in %in: !firrtl.integer) {
    }
    firrtl.module @InputProp() attributes {convention = #firrtl<convention scalarized>} {
      %o = firrtl.object @Test(in in: !firrtl.integer)
      %0 = firrtl.object.subfield %o[in] : !firrtl.class<@Test(in in: !firrtl.integer)>
      %1 = firrtl.integer 5
      firrtl.propassign %0, %1 : !firrtl.integer
    }
  }
}

[rwy7]

Thanks!

[dtzSiFive]

Please correct me, but this appears to actually be an IMDCE issue (that's already known/being worked on).