Open uenoku opened 6 months ago
hw.module @Baz(in %cond : i2, in %value : i2, out o1: i2, out o2: i2) { %0 = comb.and bin %cond, %value : i2 %1 = comb.and bin %0, %value : i2 hw.output %0, %1: i2, i2 }
Current output (canonicalization + export-verilog):
// Generated by CIRCT unknown git version module Baz( // nya.mlir:1:1 input [1:0] cond, // nya.mlir:1:19 value, // nya.mlir:1:34 output [1:0] o1, // nya.mlir:1:51 o2 // nya.mlir:1:63 ); wire [1:0] _GEN = cond & value; // nya.mlir:2:8 assign o1 = _GEN; // nya.mlir:2:8, :4:3 assign o2 = _GEN & value; // nya.mlir:2:8, :3:8, :4:3 endmodule
o2 could be just _GEN because value is a duplication. This is currently not optimized because _GEN is not flattened into o2 since _GEN is multiply used.
o2
_GEN
value
This looks to be fixed by 6903 -- are there other opportunities to address, or okay to close?
Current output (canonicalization + export-verilog):
o2
could be just_GEN
becausevalue
is a duplication. This is currently not optimized because_GEN
is not flattened intoo2
since_GEN
is multiply used.