llvm / circt

Circuit IR Compilers and Tools
https://circt.org
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[FIRRTL] LowerLayers creates empty port names, preventing round-trip #7224

Open fzi-hielscher opened 1 week ago

fzi-hielscher commented 1 week ago

When we have anonymous signals cross layer boundaries (e.g, due to CSE, like so), LowerLayers will create an FModuleOp where the port name attribute for these signals is the empty string. For the most part, this does not appear to cause any issues. But when we serialize the IR, the name is handled differently by the printers of the firrtl.module and the firrtl.instance op respectively.

Since the module argument's SSA value name cannot be empty, the port is called "arg0" in the module declaration: firrtl.module private @Example_A(in %arg0: !firrtl.uint<9>, in %reset: !firrtl.uint<1>, in %clock: !firrtl.clock) The instantiation on the other hand will just use the empty string attribute: firrtl.instance a { ... } @Example_A(in "": !firrtl.uint<9>, in reset: !firrtl.uint<1>, in clock: !firrtl.clock) Which prevents the circuit from being parsed again: error: 'firrtl.instance' op name for port 0 must be "arg0", but got ""

I don't know if it is by design or by accident that empty port names don't seem to break anything else. Are they considered legal?

(Ping @fzi-antonpaule, who found this problem)