The type of reset inferred for a module port changes the implementation of any register which uses it. Since extmodules are separately compiled modules from other circuits, it does not make sense that the reset could be inferred. We already have a verifier that public modules do not have uninferred reset types, so there should be no reason to allow this.
FIRRTL version 4.0.0
circuit Foo:
public module Foo:
input sync : UInt<1>
inst bar of Bar
connect bar.r, sync
extmodule Bar:
input r : Reset
compiles fine and Bar.r is inferred to be a synchronous reset.
dtzSiFive
commented
3 months ago
The type of reset inferred for a module port changes the implementation of any register which uses it. Since extmodules are separately compiled modules from other circuits, it does not make sense that the reset could be inferred. We already have a verifier that public modules do not have uninferred reset types, so there should be no reason to allow this.
compiles fine and
Bar.ris inferred to be a synchronous reset.