Open patrick-rivos opened 2 months ago
@llvm/issue-subscribers-backend-risc-v
Author: Patrick O'Neill (patrick-rivos)
The root cause is:
RISCVRegisterInfo::getReservedRegs
because RISCVFrameLowering::hasFP
(hasStackRealignment
returns false) returns false.MaxAlignment
to RVVStackAlign
(which is 16B) in RISCVFrameLowering::processFunctionBeforeFrameFinalized
:
https://github.com/llvm/llvm-project/blob/13d39cb6f7b20e596b66f59ebf4dba766451398b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp#L1229-L1239hasFP
returns true as MachineFrameInfo::shouldRealignStack
returns true (MaxAlignment > StackAlignment
, in which MaxAlignment
is 16B and StackAlignment
is 4B(ilp32e) or 8B(lp64e)):
https://github.com/llvm/llvm-project/blob/13d39cb6f7b20e596b66f59ebf4dba766451398b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp#L661-L667A potential fix (#101002) is to make RVV stack alignment decided by ABI just like the default stack alignment, but I think this can be ABI incompatiblity. cc @kito-cheng
Testcase:
With
-march=rv64iv -mabi=lp64e
Reduced LLVM IR:
Command/backtrace:
The same assert can also be triggered on ilp32e with
-march=rv32i_xsfvcp -mabi=ilp32e
Godbolt: https://godbolt.org/z/3j4j8eGMz
Found via fuzzer.