Open Rexicon226 opened 2 months ago
@llvm/issue-subscribers-backend-x86
Author: David Rubin (Rexicon226)
How this IR getting generated? I assume using -march=x86-64-v3 -mavx512f
will get "target-features"="+avx512f,+evex512"
.
The "+avx512f,-evex512"
is a bad combination. -evex512
requires target has +avx512vl
feature.
How this IR getting generated? I assume using
-march=x86-64-v3 -mavx512f
will get"target-features"="+avx512f,+evex512"
.The
"+avx512f,-evex512"
is a bad combination.-evex512
requires target has+avx512vl
feature.
You make a very good point. This comes from the Zig compiler, where I was setting the avx512f
flag manually, without evex512
being enabled. That was my oversight. Still, should the crash happen? What's the policy on invalid target features attr in the IR?
AFAIK, target features can be organized arbitrarily. The evex512
is the only exception. Theoretically, we can solve the crash in backend, but it doesn't have much value, because there's no such a target mapping to this combination. So we carefully handled it in Clang frontend. Other front end should do similar thing to avoid such combination.
Here's a repro of the crash with clang:
Here's a godbolt of it happening on trunk assertions: https://llvm.godbolt.org/z/aPP7dE74x
Stack Trace
``` ❯ clang-18 -c ir.ll -O3 fatal error: error in backend: Cannot select: t90: v4i1 = setcc t63, t79, setgt:ch t63: v4i32 = and t61, t91 t61: v4i32 = bitcast t86 t86: v4f32 = X86ISD::INSERTPS t72, t84, TargetConstant:i8<16> t72: v4f32 = scalar_to_vector t4 t4: f32,ch = CopyFromReg t0, Register:f32 %1 t3: f32 = Register %1 t84: v4f32 = scalar_to_vector t2 t2: f32,ch = CopyFromReg t0, Register:f32 %0 t1: f32 = Register %0 t85: i8 = TargetConstant<16> t91: v4i32,ch = X86ISD::VBROADCAST_LOAD<(load (s32) from constant-pool)> t0, t83 t83: i64 = X86ISD::WrapperRIP TargetConstantPool:i64