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Missed optimisation to take advantage of commutative SVE fmul instruction #115697

Open ktkachov opened 2 weeks ago

ktkachov commented 2 weeks ago

Example AArch64 SVE intrinsics code:

#include <arm_sve.h>

svfloat64_t svmul_x_2(svfloat64_t x, svfloat64_t y, svbool_t pg)
{
    return svmul_x(pg, svdup_f64(2), x);
}

This can generate just a singly FMUL instruction but LLVM moves the immediate 2 into a register first. https://godbolt.org/z/11aEEGoce

llvmbot commented 2 weeks ago

@llvm/issue-subscribers-backend-aarch64

Author: Kyrill Tkachov (ktkachov)

Example AArch64 SVE intrinsics code: ``` #include <arm_sve.h> svfloat64_t svmul_x_2(svfloat64_t x, svfloat64_t y, svbool_t pg) { return svmul_x(pg, svdup_f64(2), x); } ``` This can generate just a singly FMUL instruction but LLVM moves the immediate 2 into a register first. https://godbolt.org/z/11aEEGoce