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Implement the SandyBridge/Haswell machine model for x86 SSE4 and AVX. #17741

Open atrick opened 10 years ago

atrick commented 10 years ago
Bugzilla Link 17367
Version trunk
OS All
Depends On llvm/llvm-project#34991
Blocks llvm/llvm-project#31672
CC @adibiagio,@topperc,@hfinkel,@jryans,@LebedevRI,@RKSimon,@rotateright,@ZviRackover

Extended Description

Each instruction in X86InstrSSE.td needs a SchedRW list. This is a list of types defined in X86Schedule.td. If new types are added (e.g. WritePopCnt), then a SB/HWWriteRes entry should be added to X86SchedSandyBridge.td and X86SchedHaswell.td.

Once this is done we can mark the model complete. See this FIXME def SandyBridgeModel... // FIXME: SSE4 and AVX are unimplemented. This flag is set to allow // the scheduler to assign a default model to unrecognized opcodes. let CompleteModel = 0;

Without this workaround the scheduler asserts because x86 already has itinerary classes for these instructions, indicating they should be modeled by the scheduler. Since we use the new machine model for other instructions, it expects a new machine model for these too.

LLVM ERROR: DefIdx 0 exceeds machine model writes for ...

RKSimon commented 2 years ago

mentioned in issue llvm/llvm-project#34991

RKSimon commented 2 years ago

mentioned in issue llvm/llvm-project#31672

RKSimon commented 6 years ago

I think we should, I haven't been doing so as I've been trying to ensure we have full coverage before we start limiting the models but I'm intending to go back and do so for Btver2 (and maybe others like Atom+SLM) so I can flag them all as complete.

We'd also need to be on the look out for models being used for unexpected targets. For instance Haswell is being used for the KNL/KNM models (so need AVX512 coverage) and SandyBridge is being used as the Generic x86_64 so I'd say we need FULL coverage for that.

topperc commented 6 years ago

Can we use the "UnsupportedFeatures" list to suppress the checks for incomplete information on processor that don't support AVX512 for example?

RKSimon commented 6 years ago

Pinging this this old bug as I reckon its still very relevant (and not just for SandyBridge/Haswell) and I'd like to hear people's views.

We have very poor coverage of the later instruction sets (BMI, AVX512 etc.) wrt itinerary and scheduler classes meaning that not a single x86 scheduler model can set CompleteModel = 1.

Not only would it speed up bring up of new models, it'd help with debugging of scheduler failures and probably help reduce the high number of instregex entries we've ended up with that can be tricky to maintain (although I realise some are auto-generated).

Thoughts?