support AARCH32 cp15 register access by mrs/msr and name

[llvmbot]

Bugzilla Link	22794
Version	3.6
OS	Linux
Reporter	LLVM Bugzilla Contributor

Extended Description

Support ARMv7/AARCH32 cp15 register access via mrs/msr and names instead of the cryptic mrc/mcr would be nice. ARM has added support in ARMCC V5 added support for it: asm ("mrs %0, MPIDR" : "=r" (val));

so for Clang still this (cryptic) must be used: asm ("mrc p15,0,%0,c0,c0,5;" : "=r" (val));

When targeting AARCH64 the names work nicely:

asm ("mrs %0, MPIDR_EL1"=r" (val));

At some point, native supporting this for 64-bit registers via a similar mechnism would also be a nice thing. See http://community.arm.com/groups/tools/blog/2014/10/16/msrrmrrs--a-asm-macro-for-64-bit-named-registers

So the cryptic asm ("mrrc p15,0,%0,%1,c7":"=r"(val0),"=r"(val1));

can be used as this pseudo instruction: asm ("mrrs %0,%1,PAR":"=r"(val0),"=r"(val1));

[llvmbot]

@llvm/issue-subscribers-backend-aarch64

[llvmbot]

@llvm/issue-subscribers-backend-arm

[DavidSpickett]

This is about reading 64 bit co-processor registers, on 32 bit ARM, changing the label.

https://developer.arm.com/documentation/dui0473/m/arm-and-thumb-instructions/mrrc-and-mrrc2 for reference.