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[PowerPC] MIR lit test marked XFAIL for powerpc due to use of undefined physical register #30410

Open llvmbot opened 7 years ago

llvmbot commented 7 years ago
Bugzilla Link 31062
Version trunk
OS Windows NT
Reporter LLVM Bugzilla Contributor
CC @hfinkel,@nemanjai

Extended Description

test/CodeGen/MIR/Generic/branch-probabilities.ll

Machine code for function test: IsSSA, NoPHIs, TracksLiveness

Function Live Ins: %X3 in %vreg0

BB#0: derived from LLVM BB %entry Live Ins: %X3 %vreg0 = COPY %X3; G8RC:%vreg0 %vreg2 = ANDIo8 %vreg0, 1, %CR0; G8RC:%vreg2,%vreg0 %vreg1 = COPY %CR0GT; CRBITRC:%vreg1 BCn %vreg1, <BB#2>; CRBITRC:%vreg1 B <BB#1> Successors according to CFG: BB#1(0x40000000 / 0x80000000 = 50.00%) BB#2(0x40000000 / 0x80000000 = 50.00%)

BB#1: derived from LLVM BB %then Predecessors according to CFG: BB#0 ADJCALLSTACKDOWN 112, %R1<imp-def,dead>, %R1 BL8_NOP ga:@foo, <regmask %CR2 %CR3 %CR4 %F14 %F15 %F16 %F17 %F18 %F19 %F20 %F21 %F22 %F23 %F24 %F25 %F26 %F27 %F28 %F29 %F30 %F31 %R14 %R15 %R16 %R17 %R18 %R19 %R20 %R21 %R22 %R23 %R24 %R25 %R26 %R27 %R28 %R29 %R30 %R31 %X14 %X15 %X16 %X17 %X18 %X19 %X20 %X21 %X22 %X23 %X24 %X25 %X26 %X27 %X28 %X29 %X30 %X31 %CR2EQ %CR3EQ %CR4EQ %CR2GT %CR3GT %CR4GT %CR2LT %CR3LT %CR4LT %CR2UN %CR3UN %CR4UN>, %LR8<imp-def,dead>, %RM, %X2, %R1 ADJCALLSTACKUP 112, 0, %R1<imp-def,dead>, %R1 B <BB#3> Successors according to CFG: BB#3(0x80000000 / 0x80000000 = 100.00%)

BB#2: derived from LLVM BB %else Predecessors according to CFG: BB#0 ADJCALLSTACKDOWN 112, %R1<imp-def,dead>, %R1 BL8_NOP ga:@bar, <regmask %CR2 %CR3 %CR4 %F14 %F15 %F16 %F17 %F18 %F19 %F20 %F21 %F22 %F23 %F24 %F25 %F26 %F27 %F28 %F29 %F30 %F31 %R14 %R15 %R16 %R17 %R18 %R19 %R20 %R21 %R22 %R23 %R24 %R25 %R26 %R27 %R28 %R29 %R30 %R31 %X14 %X15 %X16 %X17 %X18 %X19 %X20 %X21 %X22 %X23 %X24 %X25 %X26 %X27 %X28 %X29 %X30 %X31 %CR2EQ %CR3EQ %CR4EQ %CR2GT %CR3GT %CR4GT %CR2LT %CR3LT %CR4LT %CR2UN %CR3UN %CR4UN>, %LR8<imp-def,dead>, %RM, %X2, %R1 ADJCALLSTACKUP 112, 0, %R1<imp-def,dead>, %R1 Successors according to CFG: BB#3(0x80000000 / 0x80000000 = 100.00%)

BB#3: derived from LLVM BB %end Predecessors according to CFG: BB#1 BB#2 BLR8 %LR8, %RM

End machine code for function test.

Bad machine code: Using an undefined physical register

Bad machine code: Using an undefined physical register

nemanjai commented 6 years ago

Register R2/X2 is reserved on PPC under certain conditions and not under other conditions. There isn't enough info in mir files to make that determination.

This can probably only be fixed by changing the mir format to contain further information such as MachineFunctionInfo.