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[X86] Scheduler information for FXRSTOR on Sandybridge looks bogus #35304

Open topperc opened 6 years ago

topperc commented 6 years ago
Bugzilla Link 35956
Version trunk
OS All
Blocks llvm/llvm-project#31672
CC @RKSimon

Extended Description

I highly doubt this is correct. Every other scheduler model shows an order of magnitude more uops and instructions.

def SBWriteResGroup47 : SchedWriteRes<[SBPort4,SBPort5,SBPort01,SBPort23]> { let Latency = 5; let NumMicroOps = 5; let ResourceCycles = [1,2,1,1]; } def: InstRW<[SBWriteResGroup47], (instregex "FXRSTOR")>;

topperc commented 3 years ago

mentioned in issue llvm/llvm-bugzilla-archive#35979