[MSP430][InstCombine][DAGCombine]Poor codegen for targets with no native shifts (1/8)

[llvmbot]

Bugzilla Link	44038
Version	trunk
OS	All
Reporter	LLVM Bugzilla Contributor
CC	@LebedevRI,@rotateright

Extended Description

A number of comparisons involving bit tests are converted into shifts by InstCombine and DAGCombine. However, shifts are expensive for most 8 and 16 bit targets with comparatively cheaper selects.

It is desirable that selects are emitted instead of shifts for these targets. The following cases were identified in TargetLowering and DAGCombine and were fixed by:

https://reviews.llvm.org/D69116 https://reviews.llvm.org/D69120 https://reviews.llvm.org/D69326 https://reviews.llvm.org/D70042

Cases in InstCombine remain to be fixed. In llvm-dev it has been suggested that these cases should be fixed by reversing the current canonicalisation. I am showing them in this and following reports:

REPORTED CASE:

Source code:

int testSimplifySetCC_0( int x )  // (InstCombineCasts::transformZExtICmp)
{
  return (x & 32) != 0;
}

IR code:

define i16 @testSimplifySetCC_0(i16 %x) {
entry:
  %and = lshr i16 %x, 5
  %and.lobit = and i16 %and, 1
  ret i16 %and.lobit
}

MSP430 Target code:

testSimplifySetCC_0:
    clrc
    rrc r12
    rra r12
    rra r12
    rra r12
    rra r12
    and llvm/llvm-project#373, r12
    ret

AVR Target code:

testSimplifySetCC_0:
    lsr r25
    ror r24
    lsr r25
    ror r24
    lsr r25
    ror r24
    lsr r25
    ror r24
    lsr r25
    ror r24
    andi    r24, 1
    andi    r25, 0
    ret

EXPECTED RESULT:

Source code:

int testSimplifySetCC_0( int x )  // (InstCombineCasts::transformZExtICmp)
{
  return (x & 32) != 0;
}

Expected IR code:

define dso_local i16 @testSimplifySetCC_0(i16 %x) local_unnamed_addr #0 {
entry:
  %and = and i16 %x, 32
  %cmp = icmp ne i16 %and, 0
  %conv = zext i1 %cmp to i16
  ret i16 %conv
}

Expected MSP430 Target code:

testSimplifySetCC_0:
    bit llvm/llvm-project#404, r12
    mov r2, r12
    and llvm/llvm-project#373, r12
    ret

Expected AVR Target code:

testSimplifySetCC_0:
    andi    r24, 32
    andi    r25, 0
    ldi r20, 0
    ldi r21, 0
    ldi r18, 1
    cp  r24, r20
    cpc r25, r21
    brne    LBB0_2
    ldi r18, 0
LBB0_2:
    mov r24, r18
    clr r25
    ret

[llvmbot]

changed the description

[benshi001]

AVR has gained great optimization on 8/16/32-bit shifts.

[llvmbot]

@llvm/issue-subscribers-backend-msp430

[rotateright]

Probably needs a codegen reversal: https://godbolt.org/z/4hYvjhzY3

[benshi001]

Here is contrast between avr-gcc and clang-trunk : https://godbolt.org/z/TsWTvhvv7