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thumb2, aclass, rclass, etc. ARM features not supported in clang -mcpu #52878

Closed silversquirl closed 3 months ago

silversquirl commented 2 years ago

Several ARM architecture features (and possibly for other archs too, but I only checked ARM) are not included in the table used to validate clang's -mcpu option. This makes it impossible to specify that, for example, thumb2 instructures are available on a CPU model that doesn't normally support them.

This is particularly annoying when using clang to compile assembly, as it will emit errors like this, while providing no way to enable thumb2 other than by running cc1as directly:

test.s:1:2: error: invalid instruction, any one of the following would fix this:
        mov r1, #0
        ^
test.s:1:10: note: operand must be a register in range [r0, r15]
        mov r1, #0
                ^
test.s:1:2: note: instruction requires: thumb2
        mov r1, #0
        ^
davemgreen commented 2 years ago

Can you explain more about what you are trying to do? -mcpu=cortex-m0plus+thumb2 isn't a valid combination (and I don't think should be). Depending on what you are trying to achieve, you may really want to specify a different cpu, or a different -march option that specifies an architecture with thumb2 available.

silversquirl commented 2 years ago

Cortex-M0+ supports a subset of the Thumb-2 instruction set - I'm trying to assemble a file that uses those instructions

davemgreen commented 2 years ago

The architecture is split into Armv6-m and Armv7-m. Cortex-M0+ is an Armv6-m core. Most 32bit instructions are Armv7-m. A few (BL for example, MRS and MSR, etc) are available in Armv6-m, but there are not many. This page has has an image in the "Instruction Set" section that shows some of the instructions (that are not covered up): https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/five-things-you-may-not-know-about-arm-cortex-m

MOV rn, #0 is not one of the 32bit instruction available in v6m though unfortunately, and Cortex-M0+ does not support it. It would need to use the flag setting 16bit MOVS Rn, #0 variant. If you had a Cortex-M0+ (armv6m) with thumb2 - you would just have armv7m :)

MaskRay commented 3 months ago

Working as intended as davemgreen explained. I think zig should specify a different -mcpu=.