Open felixjones opened 2 years ago
https://godbolt.org/z/Ka89GqGfj
This affects performance for ARM32 embedded systems.
No matter what flags I change, I can never get the resulting ldr to use an immediate offset. It seems to always be handled via an extra register move, and a register offset.
ldr
Clang 14.0.0 -Oz -marm -mcpu=arm7tdmi -mabi=aapcs
-Oz -marm -mcpu=arm7tdmi -mabi=aapcs
mov r1, #16 lsl r0, r0, #2 orr r1, r1, #4096 ldr r0, [r0, r1] bx lr
These two instructions could be combined into a single load immediate offset.
mov r1, #16 ... ldr r0, [r0, r1]
Re-producing C code:
int read(int idx) { const volatile int* const DATA = ( const volatile int* ) 0x1010; return DATA[idx]; }
GCC produces the desired output.
GCC 12.0.0 -Os -marm -mcpu=arm7tdmi -mabi=aapcs
-Os -marm -mcpu=arm7tdmi -mabi=aapcs
lsl r0, r0, #2 add r0, r0, #4096 ldr r0, [r0, #16] bx lr
@llvm/issue-subscribers-backend-arm
https://godbolt.org/z/Ka89GqGfj
This affects performance for ARM32 embedded systems.
No matter what flags I change, I can never get the resulting
ldr
to use an immediate offset. It seems to always be handled via an extra register move, and a register offset.Clang 14.0.0
-Oz -marm -mcpu=arm7tdmi -mabi=aapcs
These two instructions could be combined into a single load immediate offset.
Re-producing C code:
GCC produces the desired output.
GCC 12.0.0
-Os -marm -mcpu=arm7tdmi -mabi=aapcs