llc -O3 -addr-sink-using-gep=false -stress-regalloc=8 -misched=shuffle -o out.s ./tc_regscav.ll
LLVM ERROR: Error while trying to spill R11D from class ADDR64Bit: Cannot scavenge register without an emergency spill slot!
'-stress-regalloc=8' limits the number of registers in each register class to 8:
This is changed in RegisterClassInfo.cpp: 'RCI.NumRegs = StressRA'.
This test case is apparently needing register scavenging, and in RegScavenger::scavengeRegisterBackwards() I see that 'AllocationOrder = RC.getRawAllocationOrder(MF)' is used, which includes the full register class, which is a little weird and makes me wonder if -stress-regalloc is broken (it was added 10 years ago by Jakob Stoklund Olesen).
It picks $r11 and then for some reason runs into the assertion above.
-stress-regalloc is really crude and only really used by the actual allocation. The post-RA uses like the scavengers don't consider it / RegisterClassInfo
testcase.tar.gz
llc -O3 -addr-sink-using-gep=false -stress-regalloc=8 -misched=shuffle -o out.s ./tc_regscav.ll LLVM ERROR: Error while trying to spill R11D from class ADDR64Bit: Cannot scavenge register without an emergency spill slot!
'-stress-regalloc=8' limits the number of registers in each register class to 8:
This is changed in RegisterClassInfo.cpp: 'RCI.NumRegs = StressRA'.
This test case is apparently needing register scavenging, and in RegScavenger::scavengeRegisterBackwards() I see that 'AllocationOrder = RC.getRawAllocationOrder(MF)' is used, which includes the full register class, which is a little weird and makes me wonder if -stress-regalloc is broken (it was added 10 years ago by Jakob Stoklund Olesen).
It picks $r11 and then for some reason runs into the assertion above.