Open MattPD opened 2 years ago
@llvm/issue-subscribers-backend-aarch64
I'll have to investigate to confirm details but in general SVE VLS code generation of 128bit and smaller vectors is not well tested and typically only enabled for a handful (but not all) of the cases where SVE has a benefit over NEON. The lowering is controlled via useSVEForFixedLengthVectorVT
which takes a flag to say whether it should also return true for NEON sized (i.e. 128 or 64 bit) vectors.
With that said, here we're talking about <2 x half>
vectors which are not currently considered type legal for NEON or SVE and so were running into legalisation issues before we get to the phase that would lower to SVE. Looking at the backtrace I'm wondering if we're running out of stack space due to infinite recursion?
Encountering an ICE after removing NEON preference in
useSVEForFixedLengthVectors
for 128-bit vector register size SVE code generation.Context: There's currently a
>= 256
vector size restriction inuseSVEForFixedLengthVectors
(in "llvm/lib/Target/AArch64/AArch64Subtarget.h").As an experiment I've relaxed it in two different ways, by changing the line in question to
return hasSVE() && getMinSVEVectorSizeInBits() >= 128;
orreturn hasSVE();
(with the same effect).I've then run the build of the modified compiler on the AArch64 LIT tests, encountering an ICE for the following test: https://github.com/llvm/llvm-project/blob/main/llvm/test/CodeGen/AArch64/sve-fixed-length-masked-gather.ll
Compilation using either
clang
orllc
together with the assumed 128-bit SVE register size is sufficient to trigger the ICE:This function alone is sufficient to trigger the ICE:
Removing the
vscale_range(2,0)
attribute or changing it tovscale_range(1,0)
has no impact (i.e., the ICE still occurs).Here's the output from the ICE in question (note the cyclic pattern of function calls in SelectionDAG):
I'm wondering, would you happen to know whether SVE code generation for the targets with 128-bit SVE registers is meant to be supported--and, possibly, would modifying
useSVEForFixedLengthVectors
as above be the proper way to go about it or could there be any remaining checks that need to be changed, e.g., inAArch64TargetLowering::useSVEForFixedLengthVectorVT
(https://github.com/llvm/llvm-project/blob/6f4773f06428d16cb4716e9d1ba590d8c2ff7596/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp#L5628-L5630)?cc @paulwalker-arm @sdesmalen-arm @stevesuzuki-arm (in case it's relevant to https://github.com/halide/Halide/pull/6781)