Open Amanieu opened 1 year ago
@llvm/issue-subscribers-backend-risc-v
This seems to be a generic problem in DAGTypeLegalizer::ExpandShiftWithUnknownAmountBit, it assumes it can just blindly select both cases (a1 < 64, a1 >= 64) rather than actually having a condition based on it. This is only correct in the case that those themselves are well-defined (poison allowed).
(https://godbolt.org/z/Yd1dqr9nn shows the problem (they look more different only due to scheduling) on i386, arm and riscv32).
Candidate patch https://reviews.llvm.org/D134684
LLVM IR:
This generates this call to
__ashldi3
at the start of the function. The value ina2
passed to__ashldi3
is out of range if the shift amount is less than 64. The documentation for__ashldi3
explicitly says that the shift amount must be between 0 and 63 inclusive.