[AArch64] Crash in the Instruction Selection

[vfdff]

case, https://gcc.godbolt.org/z/96K3n3xfx

define i8 @andv_nxv2i8(<vscale x 2 x i1> %pg, <vscale x 2 x i8> %a) {
  %res = call i8 @llvm.aarch64.sve.andv.nxv2i8(<vscale x 2 x i1> zeroinitializer, <vscale x 2 x i8> zeroinitializer)
  ret i8 %res
}

declare i8 @llvm.aarch64.sve.andv.nxv2i8(<vscale x 2 x i1>, <vscale x 2 x i8>)

[llvmbot]

@llvm/issue-subscribers-backend-aarch64

[vfdff]

record the crash message as it seems change with different version，and now it is

2.  Running pass 'AArch64 Instruction Selection' on function '@andv_nxv2i8'
#0 0x00005617f982711f llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/opt/compiler-explorer/clang-trunk/bin/llc+0x31f911f)
#1 0x00005617f9824b94 SignalHandler(int) Signals.cpp:0:0
#2 0x00007feebd2fe420 __restore_rt (/lib/x86_64-linux-gnu/libpthread.so.0+0x14420)
#3 0x00005617f72dee21 llvm::AArch64TargetLowering::addTypeForNEON

[hamza-spl]

Hi,

Where did you get this IR code ? I'm asking because I don't think the intrinsic llvm.aarch64.sve.andv will be generated in any case with the second argument <vscale x 2 x i8>, otherwise its a bug somewhere else in the IR generation. Actually all SVE reduction intrinsics llvm.aarch64.sve.{addv,uaddv,smaxv,sminv,umaxv,uminv,andv,orv,eorv,} are only supported with the following types: <vscale x 16 x i8>, <vscale x 8 x i16>, <vscale x 4 x i32>, <vscale x 2 x i64>, with the corresponding predicated vectors (<vscale x 16 x i1>, ...), and maps normally to the corresponding SVE reduction intrinsics defined in the ACLE documentation.

It will be nice if you could provide the code that generated this IR ?

Regards.

[vfdff]

oh, thanks, this is duplicate with #56142, and typically the SVE intrinsics only support legal types.