[M68k] Missing memory addressing modes for codegen

[mshockwave]

Right now we only support a subset of all memory addressing modes. Though the current set of addressing modes will suffice to codegen most of the code, some of the missing addressing modes can lead to better codegen qualities in certain cases. More importantly, AsmParser and Disassembler depend on these operand declarations too.

Adapted from a similar table in M68kInstrFormat.td originally written by Arytom, below is a table of current supporting status for all memory addressing modes. I thought it might be a good idea to track the progress of these addressing modes using this table.

Form	Letter	CodeGen Support	Shorthand / Description
(An)	j	Y	ARI: address register indirect
(An)+	o	partial: ISel function not implemented	ARIPI: address register indirect with postincrement
-(An)	e	partial: ISel function not implemented	ARIPD: address register indirect with predecrement
(d,An)	p	Y	ARID: address register indirect with displacement
(d,An,Xn.L)	f	Y	ARII: address register indirect with index and scale == 1
(d,An,Xn.W)	F	N	ARII: address register indirect with index and scale == 1
(d,An,Xn.L,SCALE)	g	N	ARII: address register indirect with index
(d,An,Xn.W,SCALE)	G	N	ARII: address register indirect with index
([bd,An],Xn.L,SCALE,od)	u	N	memory indirect postindexed mode
([bd,An],Xn.W,SCALE,od)	U	N	memory indirect postindexed mode
([bd,An,Xn.L,SCALE],od)	v	N	memory indirect preindexed mode
([bd,An,Xn.W,SCALE],od)	V	N	memory indirect preindexed mode
abs.L	b	Y	AL: absolute long address
abs.W	B	partial: ISel function not implemented	AS: absolute short address
(d,PC)	q	Y	PCD: program counter with displacement
(d,PC,Xn.L)	k	Y	PCI: program counter with index and scale == 1
(d,PC,Xn.W)	K	N	PCI: program counter with index and scale == 1
(d,PC,Xn.L,SCALE)	l	N	PCI: program counter with index
(d,PC,Xn.W,SCALE)	L	N	PCI: program counter with index
([bd,PC],Xn.L,SCALE,od)	x	N	program counter memory indirect postindexed mode
([bd,PC],Xn.W,SCALE,od)	X	N	program counter memory indirect postindexed mode
([bd,PC,Xn.L,SCALE],od)	y	N	program counter memory indirect preindexed mode
([bd,PC,Xn.W,SCALE],od)	Y	N	program counter memory indirect preindexed mode

For explanations of these addressing modes, please refer to Section 2.2 in the M68k Programmers' Manual.

I think we can start from the low-hanging fruits like 'o', 'e', and 'B' to finish their missing functionalities first.

[llvmbot]

@llvm/issue-subscribers-backend-m68k

[RKSimon]

I'm not sure if there's any current plan to support ColdFire CPUs, but being able to enable/disable specific addressing modes would definitely assist with it: https://www.microapl.com/Porting/ColdFire/cf_68k_diffs.html

[mshockwave]

I'm not sure if there's any current plan to support ColdFire CPUs, but being able to enable/disable specific addressing modes would definitely assist with it: https://www.microapl.com/Porting/ColdFire/cf_68k_diffs.html

Right, and I think we need to do that (enable/disable specific addressing modes) anyway since some of the addressing modes are not supported until 68020 (e.g. memory indirect addressing). I think the only way to do so right now is using predicates (e.g. AtLeast68020) on instruction declarations, which is tbh not really hard owing to how we factor out operands with different addressing modes.