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[X86] X86SchedAlderlakeP.td is missing dependency breaking idioms #61003

Open RKSimon opened 1 year ago

RKSimon commented 1 year ago

CC @phoebewang @HaohaiWen

The alderlake-p model is currently missing patterns for dependency breaking instructions (zero/allones idioms, move elimination etc.) - some of this can probably be just copied from X86SchedIceLake.td (which itself still misses many cases).

llvmbot commented 1 year ago

@llvm/issue-subscribers-backend-x86

HaohaiWen commented 1 year ago

Do you mean something like this?

def ICXWriteZeroLatency : SchedWriteRes<[]> {
  let Latency = 0;
}

def ICXWriteZeroIdiom : SchedWriteVariant<[
    SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [ICXWriteZeroLatency]>,
    SchedVar<NoSchedPred,                          [WriteALU]>
]>;
def : InstRW<[ICXWriteZeroIdiom], (instrs SUB32rr, SUB64rr,
                                          XOR32rr, XOR64rr)>;
RKSimon commented 1 year ago

Yes, plus various vector instructions - I think IceLake/AlderLake also recognize some AllOnesIdioms etc. as well - Agner usually has a pretty thorough list