Open Amanieu opened 1 year ago
@llvm/issue-subscribers-backend-risc-v
I'm trying to fix this issue and https://github.com/rust-lang/rust/issues/80608 https://github.com/rust-lang/rust/issues/127269 which I believe have the same root cause.
So far I've narrowed it down to here https://github.com/llvm/llvm-project/blob/main/llvm/lib/Object/ModuleSymbolTable.cpp#L96
it creates an ASM parser with empty (""
) target features, so parsing the ASM fails. The target requires "+vfp3d16"
for target features. I've confirmed if I hardcode that in there the error goes away. However, I don't know what the right fix would be. How can I obtain the target features from there? The module only contains the target triple.
Any hints would be appreciated.
Also noting from the other thread: this appears not JUST to be a RISC-V relevant issue, it's applicable to any target that requires target features. The issue linked in https://github.com/rust-lang/rust/issues/127269 is for an Arm Cortex-R processor.
test.c
Output
The D feature is enabled by default on
riscv64-unknown-linux-gnu
, so this error should normally not be emitted.However compilation still completes successfully (exit code 0) and produces valid LLVM bitcode in
test.o
.Similar bug in rustc: https://github.com/rust-lang/rust/issues/80608