[aarch64] gcc choose less latency instruction than clang

[vfdff]

• Test case, see https://gcc.godbolt.org/z/T1qzcWjTK

  vec mla1(vec v0, vec v1, int v2)
  {
  return v0 - v1 * v2;
  }

• GCC: fmov + mls

      fmov    s31, w0
      mls     v0.4s, v1.4s, v31.s[0]
      ret

• LLVM: dup + mls

      dup     v2.4s, w0
      mls     v0.4s, v2.4s, v1.4s
      ret

  For some targets (I'm not sure all targets), the latency of dup instruction from scalar register to vector register is much more than 1, while the latency of fmov from scalar register to float register is usual 1, so the GCC's assemble is better.

[llvmbot]

@llvm/issue-subscribers-backend-aarch64

[vfdff]

may be similar to https://reviews.llvm.org/D126632

[vfdff]

a simliar cases for mull, https://gcc.godbolt.org/z/Pzvon7Yqv