Closed HazyFish closed 1 year ago
@DataCorrupted
@llvm/issue-subscribers-backend-risc-v
Somehow extload from f16 to i64 is legal.
Somehow extload from f16 to i64 is legal.
The table for legality defaults to all 0s which means Legal. Nothing makes it not legal. I'm working on a patch.
OK. FYI, I just added two lines to fix this (extload from f16 to i32 has the same problem):
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 2ef55d6d3b42..0a9012df5933 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -425,6 +425,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::BR_CC, MVT::f32, Expand);
setOperationAction(FPOpToExpand, MVT::f32, Expand);
setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
+ setLoadExtAction(ISD::EXTLOAD, MVT::i32, MVT::f16, Expand);
setTruncStoreAction(MVT::f32, MVT::f16, Expand);
setOperationAction(ISD::IS_FPCLASS, MVT::f32, Custom);
setOperationAction(ISD::BF16_TO_FP, MVT::f32, Custom);
@@ -464,6 +465,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setTruncStoreAction(MVT::f64, MVT::f32, Expand);
setOperationAction(FPOpToExpand, MVT::f64, Expand);
setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
+ setLoadExtAction(ISD::EXTLOAD, MVT::i64, MVT::f16, Expand);
setTruncStoreAction(MVT::f64, MVT::f16, Expand);
setOperationAction(ISD::IS_FPCLASS, MVT::f64, Custom);
setOperationAction(ISD::BF16_TO_FP, MVT::f64, Custom);
OK. FYI, I just added two lines to fix this (extload from f16 to i32 has the same problem):
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 2ef55d6d3b42..0a9012df5933 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -425,6 +425,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM, setOperationAction(ISD::BR_CC, MVT::f32, Expand); setOperationAction(FPOpToExpand, MVT::f32, Expand); setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand); + setLoadExtAction(ISD::EXTLOAD, MVT::i32, MVT::f16, Expand); setTruncStoreAction(MVT::f32, MVT::f16, Expand); setOperationAction(ISD::IS_FPCLASS, MVT::f32, Custom); setOperationAction(ISD::BF16_TO_FP, MVT::f32, Custom); @@ -464,6 +465,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM, setTruncStoreAction(MVT::f64, MVT::f32, Expand); setOperationAction(FPOpToExpand, MVT::f64, Expand); setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand); + setLoadExtAction(ISD::EXTLOAD, MVT::i64, MVT::f16, Expand); setTruncStoreAction(MVT::f64, MVT::f16, Expand); setOperationAction(ISD::IS_FPCLASS, MVT::f64, Custom); setOperationAction(ISD::BF16_TO_FP, MVT::f64, Custom);
I'm going to fix LegalizeDAG to not mix int and FP types when trying to legalize extending loads. Targets shouldn't have to mark non-sensical type actions to prevent this.
Description
When
d
(Standard Extension for Double-Precision Floating-Point) feature is on, the following code crashes RISCV backend with assertion errorVT.isInteger() == MemVT.isInteger() && "Cannot convert from FP to Int or Int -> FP!"
.Cause
https://github.com/llvm/llvm-project/blob/b10899d869954e1426684cbc20a43d7303075d49/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp#L8210-L8229
The param
VT
isi64
type andMemVT
isf16
, which caused the assertion to fail.Minimal Reproduction
https://godbolt.org/z/EK698bYWv
Code
Stack Trace