Assert when combining store in RISCVTargetLowering::PerformDAGCombine

[bjope]

This IR

define void @bar(ptr %p, ptr %q) {
  %v = insertelement <64 x i64> zeroinitializer, i64 0, i32 1
  %trunc = trunc <64 x i64> %v to <64 x i1>
  %p1 = getelementptr i8, ptr %p, i32 0
  %p2 = getelementptr i8, ptr %p, i32 8
  store <64 x i1> %trunc, ptr %p1
  store <8 x i8> zeroinitializer, ptr %p2
  ret void
}

And running llc -mtriple riscv64 -mattr=+zve64x results in

llc: /root/llvm-project/llvm/lib/Support/APInt.cpp:370: void llvm::APInt::insertBits(const llvm::APInt&, unsigned int): Assertion `(subBitWidth + bitPosition) <= BitWidth && "Illegal bit insertion"' failed.
PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace.
Stack dump:
0.  Program arguments: /opt/compiler-explorer/clang-assertions-trunk/bin/llc -o /app/output.s -x86-asm-syntax=intel -mtriple riscv64 -mattr=+zve64x <source>
1.  Running pass 'Function Pass Manager' on module '<source>'.
2.  Running pass 'RISC-V DAG->DAG Pattern Instruction Selection' on function '@bar'
 #0 0x000000000339de18 llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/opt/compiler-explorer/clang-assertions-trunk/bin/llc+0x339de18)
 #1 0x000000000339b70c SignalHandler(int) Signals.cpp:0:0
 #2 0x00007f9477089420 __restore_rt (/lib/x86_64-linux-gnu/libpthread.so.0+0x14420)
 #3 0x00007f9476b4c00b raise (/lib/x86_64-linux-gnu/libc.so.6+0x4300b)
 #4 0x00007f9476b2b859 abort (/lib/x86_64-linux-gnu/libc.so.6+0x22859)
 #5 0x00007f9476b2b729 (/lib/x86_64-linux-gnu/libc.so.6+0x22729)
 #6 0x00007f9476b3cfd6 (/lib/x86_64-linux-gnu/libc.so.6+0x33fd6)
 #7 0x00000000032bde80 llvm::APInt::insertBits(llvm::APInt const&, unsigned int) (/opt/compiler-explorer/clang-assertions-trunk/bin/llc+0x32bde80)
 #8 0x00000000018a8137 llvm::RISCVTargetLowering::PerformDAGCombine(llvm::SDNode*, llvm::TargetLowering::DAGCombinerInfo&) const (/opt/compiler-explorer/clang-assertions-trunk/bin/llc+0x18a8137)

This was found when experimenting to create a reproducer for a different bug seen after https://reviews.llvm.org/D156349 . So it's handwritten IR. No idea if this would be common in reality.

Here is a Godbolt example: https://godbolt.org/z/Yo5d7o84q

[llvmbot]

@llvm/issue-subscribers-backend-risc-v

[wangpc-pp]

--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -13475,11 +13475,12 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
         ISD::isBuildVectorOfConstantSDNodes(Val.getNode())) {
       // Get the constant vector bits
       APInt NewC(Val.getValueSizeInBits(), 0);
+      uint64_t EleSize = Val.getScalarValueSizeInBits();
       for (unsigned i = 0; i < Val.getNumOperands(); i++) {
         if (Val.getOperand(i).isUndef())
           continue;
-        NewC.insertBits(Val.getConstantOperandAPInt(i),
-                        i * Val.getScalarValueSizeInBits());
+        NewC.insertBits(Val.getConstantOperandAPInt(i).trunc(EleSize),
+                        i * EleSize);
       }