[M68k] Exception Vector Table

[thankfulmachine]

Description

The exception vector table exists in the first 1024 bytes of the address space, 256 long words in total. The first two are predefined to the the initial supervisor stack pointer and the initial program counter respectively. Clements, p. 448

Some are unassigned or reserved so, for forward compatibility, they should not be used as they can be defined in later 680x0 generations. See below for more information.

Tying Declarations to EVT Slots

Clang currently requires a single numeric argument to the interrupt attribute, presumably for the interrupt vector number, but this may not necessarily be required. It also arbitrarily limits the number to around 30, from what I can tell.

Two usability points:

1. It would be nice if the user did not have to know the exact interrupt number, but maybe this isn't possible without a linker script.
2. The user should be able to reuse the same function in multiple slots in the table.

GCC has dealt with this via linker script in the past, as shown in this example linker script from m68k_bare_metal. I like this solution pretty well.

What can we do better?

Default Exception Implementation(s)

Some of these slots must be populated. What is the default implementation for an exception? rte? stop? It might be good to let the user decide somehow (well known decl name?). FWIW, the bare metal project mentioned above uses:

stop #2700
bra .

Example exception vector table (68000)

Vector Number	Address	Description
0	000	Initial supervisor stack pointer
-	004	Initial program counter
2	008	Bus error
3	00C	Address error
4	010	Illegal instruction
5	014	Divide by zero
6	018	CHK instruction
7	01C	TRAPV instruction
8	020	Privilege violation
9	024	Trace
10	028	Line A (1010) emulator
11	02C	Line F (1111) emulator
12	030	Unassigned, reserved
13	034	Unassigned, reserved
14	038	Unassigned, reserved
15	03C	Uninitialized interrupt vector
16	040	Unassigned, reserved
17	044	Unassigned, reserved
18	048	Unassigned, reserved
19	04C	Unassigned, reserved
20	050	Unassigned, reserved
21	054	Unassigned, reserved
22	058	Unassigned, reserved
23	05C	Unassigned, reserved
24	060	Spurious interrupt
25	064	Level 1 interrupt autovector
26	068	Level 2 interrupt autovector
27	06C	Level 3 interrupt autovector
28	070	Level 4 interrupt autovector
29	074	Level 5 interrupt autovector
30	078	Level 6 interrupt autovector
31	07C	Level 7 interrupt autovector
32-47	080-0BC	TRAP 0-15 instruction vector
48-63	0C0-0FC	Unassigned, reserved ⭐️
64-255	100-3FC	User interrupt vectors

⭐️ These are filled with FPU and MMU conditions for later 680x0.

[thankfulmachine]

CC @mshockwave

[llvmbot]

@llvm/issue-subscribers-backend-m68k

[glaubitz]

CC @mshockwave @0x59616e

[0x59616e]

I'll embark on this.

[0x59616e]

I guess one of the tasks of this issue and #64833 is to implement the calling convention of interrupt handler, right ? Is there any document or code regarding this ?

[glaubitz]

I guess one of the tasks of this issue and #64833 is to implement the calling convention of interrupt handler, right ? Is there any document or code regarding this ?

Did you check the »Literature« project here? https://github.com/M680x0/Literature

[glaubitz]

@0x59616e In case the literature provided does not answer your questions, I can reach out to some m68k experts on the mailing lists.

Let me know.

[0x59616e]

It seems that it doesn't require anything but a RTE at the end of the instruction sequence.