Open gyuminb opened 1 year ago
@llvm/issue-subscribers-backend-aarch64
Author: None (gyuminb)
Does it give consistent results with -fno-strict-aliasing?
Does it give consistent results with -fno-strict-aliasing?
Thank you for the suggestion, topperc.
While the use of -fno-strict-aliasing provides consistent results, it's worth noting that the observed issue is specific to the ARM64 architecture when compiled without this option. On other architectures like x86-64, and with other compilers like GCC, the behavior is consistent and as expected, even without the -fno-strict-aliasing flag.
This specificity suggests that there might be a deeper underlying issue with the ARM64 architecture optimization in Clang-18, rather than just a generic strict aliasing concern. Would appreciate further insights into this matter.
I've taken a brief look at the Arm and AArch64 code. They both generate the same IL
{code}
define hidden i32 @main() local_unnamed_addr #0 {
%1 = alloca ptr, align 8
%2 = load i64, ptr @main_union, align 8, !tbaa !5
%3 = tail call i32 (ptr, ...) @__2printf(ptr noundef nonnull dereferenceable(1) @.str, i64 noundef %2) #2
call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %1) #2
store ptr @ptr_val1, ptr %1, align 8, !tbaa !8
store i64 1311768467463794175, ptr @main_union, align 8, !tbaa !10
store ptr %1, ptr @triple_ptr, align 8, !tbaa !8
%4 = load ptr, ptr @ptr_val1, align 8, !tbaa !8
store i32 0, ptr %4, align 4, !tbaa !12
%5 = load i64, ptr @main_union, align 8, !tbaa !5
%6 = call i32 (ptr, ...) @__2printf(ptr noundef nonnull dereferenceable(1) @.str, i64 noundef %5) #2
call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %1) #2
ret i32 0
}
I'm not well versed enough in TBAA to trace all this through, although I note that store of 0 and the store of the initializing value have different values of TBAA. An expert may be able to help point out an aliasing problem.
Looking at the generated code between Arm and AArch64 it looks like this is a matter of scheduling. The write of 0 happens before the write of the initializing value which removes it. By selecting a different CPU with a different scheduling model like cortex-53 the write of 0 happens after the initialization so you get the answer you expect.
I think this adds some weight to an aliasing problem rather than a specific bug in the AArch64 backend although I couldn't be sure. I normally work on linkers.
Description:
When compiling the provided PoC on ARM64 architecture with Clang-18, there seems to be a pointer dereference optimization issue. The behavior of the code changes based on different optimization levels, and it's influenced by the data patterns used as well as the structure of adjacent
printf
calls. For some data patterns, the issue is observed across optimization levelsO1
toO3
. Intriguingly, when replacing two identicalprintf
calls with two distinct ones before and after the problematic line, the issue exclusively appears inO3
. It suggests that the optimization is influenced not just by data patterns but also by the presence and structure of adjacent print functions.Environment:
O1
,O2
, andO3
depending on the data patterns used. For patterns like0x123456789abcdeff
, the issue can be observed from to , but for patterns like0x1234567fffffffff
, it exclusively appears at .PoC:
Expected Behavior:
The value of
main_union.u_val5
should be consistent across different optimization levels after the pointer dereference operation.Observed Behavior:
he value of
main_union.u_val5
changes depending on the optimization level, data patterns, and the structure of adjacentprintf
calls.Analysis:
The optimization seems to overlook the `(triple_ptr) = 0UL;
** operation. The discrepancy in output, depending on the structure of **
printf** calls and data patterns, indicates a misoptimization during the compilation process. Notably, when changing the structure of the **
printf** statement or using a data pattern with repeating digits, the issue singularly appears in **
O3`** optimization level. This brings to light the complex nature of this optimization bug that is sensitive to both the data patterns and surrounding code structures.Steps to Reproduce:
O1
,O2
, andO3
).printf
structure.Evidence:
The following output showcases the behavior for various optimization levels:
What's intriguing is that when we replace two identical
printf
calls before and after the problematic line with two distinctprintf
calls, such as:and
the issue only manifests at
O3
optimization level.Conclusion:
Across different optimization levels (
O1
toO3
), there is a clear evidence of a bug likely resulting from incorrect compiler optimization. The unique scenarios under which this bug emerges, especially when altering theprintf
structures or data patterns, further underline the unpredictable nature of this issue. This bug certainly requires attention to ensure consistent and correct behavior across all optimization levels.