[X86] llvm.lrint.vxi32.vxf64 fails to codegen

[artagnon]

This issue was reported by @mstorsjo on #69945, and is a blocker for re-landing the patch. The following minimal reproduction has been extracted:

define <8 x i32> @lrint_v8f64(<8 x double> %x) {
  %a = call <8 x i32> @llvm.lrint.v8i32.v8f64(<8 x double> %x)
  ret <8 x i32> %a
}
declare <8 x i32> @llvm.lrint.v8i32.v8f64(<8 x double>)

When built as follows:

$ llc -mtriple=i686-unknown -mattr=sse2 repro.ll

There is an assertion in SelectionDAG:

llc: /home/swtoolsteam/rarm/riscv-sdk-llvm/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h:160: const llvm::SDValue& llvm::DAGTypeLegalizer::getSDValue(llvm::DAGTypeLegalizer::TableId&): Assertion `Id && "TableId should be non-zero"' failed.

The scalar version of the same program:

define i32 @lrint_f64(double %x) {
  %a = call i32 @llvm.lrint.i32.f64(double %x)
  ret i32 %a
}
declare i32 @llvm.lrint.i32.f64(double)

Works just fine.

Moreover, an f32 variant of the same program:

define <8 x i32> @lrint_v8f32(<8 x float> %x) {
  %a = call <8 x i32> @llvm.lrint.v8i32.v8f32(<8 x float> %x)
  ret <8 x i32> %a
}
declare <8 x i32> @llvm.lrint.v8i32.v8f32(<8 x float>)

Works just fine.

The root cause of the issue is a bug or deficiency in 98c90a1 (ISel: introduce vector ISD::LRINT, ISD::LLRINT; custom RISCV lowering).

[llvmbot]

@llvm/issue-subscribers-backend-x86

Author: Ramkumar Ramachandra (artagnon)

This issue was reported by @mstorsjo on #69945, and is a blocker for re-landing the patch. The following minimal reproduction has been extracted: ```llvm define <8 x i32> @lrint_v8f64(<8 x double> %x) { %a = call <8 x i32> @llvm.lrint.v8i32.v8f64(<8 x double> %x) ret <8 x i32> %a } declare <8 x i32> @llvm.lrint.v8i32.v8f64(<8 x double>) ``` When built as follows: ``` $ llc -mtriple=i686-unknown -mattr=sse2 repro.ll ``` There is an assertion in SelectionDAG: ``` llc: /home/swtoolsteam/rarm/riscv-sdk-llvm/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h:160: const llvm::SDValue& llvm::DAGTypeLegalizer::getSDValue(llvm::DAGTypeLegalizer::TableId&): Assertion `Id && "TableId should be non-zero"' failed. ``` The scalar version of the same program: ```llvm define i32 @lrint_f64(double %x) { %a = call i32 @llvm.lrint.i32.f64(double %x) ret i32 %a } declare i32 @llvm.lrint.i32.f64(double) ``` Works just fine. Moreover, an f32 variant of the same program: ```llvm define <8 x i32> @lrint_v8f32(<8 x float> %x) { %a = call <8 x i32> @llvm.lrint.v8i32.v8f32(<8 x float> %x) ret <8 x i32> %a } declare <8 x i32> @llvm.lrint.v8i32.v8f32(<8 x float>) ``` Works just fine. The root cause of the issue is a bug or deficiency in 98c90a1 (ISel: introduce vector ISD::LRINT, ISD::LLRINT; custom RISCV lowering).

[artagnon]

cc: @RKSimon, @topperc.