Closed patrick-rivos closed 6 months ago
@llvm/issue-subscribers-backend-risc-v
Author: Patrick O'Neill (patrick-rivos)
Looks like we create a gather with a vector of i1 index vector.
I think this will fix it
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 7da074e055a7..2d5ca3341ab7 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -20044,7 +20044,8 @@ bool RISCVTargetLowering::shouldRemoveExtendFromGSIndex(SDValue Extend,
// zero extended
return Extend.getOpcode() == ISD::ZERO_EXTEND &&
isTypeLegal(Extend.getValueType()) &&
- isTypeLegal(Extend.getOperand(0).getValueType());
+ isTypeLegal(Extend.getOperand(0).getValueType()) &&
+ Extend.getOperand(0).getValueType().getVectorElementType() != MVT::i1;
}
bool RISCVTargetLowering::shouldConvertFpToSat(unsigned Op, EVT FPVT,
@lukel97 @yetingk @wangpc-pp any of you able to verify my proposed fix and make a PR?
@topperc Will take a look now
Testcase:
LLVM IR:
Backtrace:
Godbolt: https://godbolt.org/z/c8v8h9fxo
Found via fuzzer