[DAG] Failure to recognise ISD::AVGFLOORS -> ISD::AVGFLOORU fold for non-negative arguments

[RKSimon]

https://rust.godbolt.org/z/ejh1bh97q

Pulled out of Hacker's Delight - if a signed floor average is between known non-negative arguments then the unsigned variant can be used instead, to potentially allow further simplification in the future.

(Sorry only aarch64 has decent ISD::AVG coverage atm):

define <8 x i16> @uhadd_in_disguise(<8 x i16> %a0, <8 x i16> %a1) {
  %m0 = and <8 x i16> %a0, <i16 510, i16 510, i16 510, i16 510, i16 510, i16 510, i16 510, i16 510>
  %m1 = and <8 x i16> %a1, <i16 510, i16 510, i16 510, i16 510, i16 510, i16 510, i16 510, i16 510>
  %r = call <8 x i16> @llvm.aarch64.neon.shadd.v8i16(<8 x i16> %m0, <8 x i16> %m1)
  ret <8 x i16> %r
}
declare <8 x i16> @llvm.aarch64.neon.shadd.v8i16(<8 x i16>, <8 x i16>)

uhadd_in_disguise:                      // @uhadd_in_disguise
        mov     w8, #510                        // =0x1fe
        dup     v2.8h, w8
        and     v0.16b, v0.16b, v2.16b
        and     v1.16b, v1.16b, v2.16b
        shadd   v0.8h, v0.8h, v1.8h     // <--- FIXME - could be uhadd
        ret

CC @davemgreen

[llvmbot]

Hi!

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If you have any further questions about this issue, don't hesitate to ask via a comment in the thread below.

[llvmbot]

@llvm/issue-subscribers-good-first-issue

Author: Simon Pilgrim (RKSimon)

https://rust.godbolt.org/z/ejh1bh97q Pulled out of Hacker's Delight - if a signed floor average is between known non-negative arguments then the unsigned variant can be used instead, to potentially allow further simplification in the future. (Sorry only aarch64 has decent ISD::AVG coverage atm): ```ll define <8 x i16> @uhadd_in_disguise(<8 x i16> %a0, <8 x i16> %a1) { %m0 = and <8 x i16> %a0, <i16 510, i16 510, i16 510, i16 510, i16 510, i16 510, i16 510, i16 510> %m1 = and <8 x i16> %a1, <i16 510, i16 510, i16 510, i16 510, i16 510, i16 510, i16 510, i16 510> %r = call <8 x i16> @llvm.aarch64.neon.shadd.v8i16(<8 x i16> %m0, <8 x i16> %m1) ret <8 x i16> %r } declare <8 x i16> @llvm.aarch64.neon.shadd.v8i16(<8 x i16>, <8 x i16>) ``` ```asm uhadd_in_disguise: // @uhadd_in_disguise mov w8, #510 // =0x1fe dup v2.8h, w8 and v0.16b, v0.16b, v2.16b and v1.16b, v1.16b, v2.16b shadd v0.8h, v0.8h, v1.8h // <--- FIXME - could be uhadd ret ``` CC @davemgreen

[chansuke]

Hi. I would like to work on this

[RKSimon]

Thanks @chansuke - I think ISD::AVGCEILS -> ISD::AVGCEILU can be performed in the same way.

I'd expect both of these to be handled in DAGCombiner::visitAVG

[RKSimon]

@chansuke reverse-ping - any progress?

[chansuke]

@RKSimon No progress yet.Start working this weekend🙏

[RKSimon]

@chansuke ping?

[chansuke]

@RKSimon I will resume work on this starting tomorrow.

[RKSimon]

You should be able to create very similar patterns to these: https://github.com/llvm/llvm-project/blob/fae31e283203da9a4a3225e2d016e245d4887c2f/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp#L5280:L5293

[chansuke]

@RKSimon thanks

[chansuke]

@RKSimon I have added the implementation. How can I test it?

[RKSimon]

Running ninja check-llvm-codegen should find any cases that are already committed - we will then need to add additional test coverage, probably in aarch64 and x64 tests