Open chenzheng1030 opened 6 months ago
Optimized legalized selection DAG: %bb.0 'testDoubleword:entry'
SelectionDAG has 19 nodes:
t0: ch,glue = EntryToken
t10: i32,ch = CopyFromReg t0, Register:i32 %4
t21: i32 = shl t10, Constant:i32<1>
t2: v2i64,ch = CopyFromReg t0, Register:v2i64 %0
t19: v4i32 = bitcast t2
t4: i32,ch = CopyFromReg t0, Register:i32 %1
t22: v4i32 = insert_vector_elt t19, t4, t21
t6: i32,ch = CopyFromReg t0, Register:i32 %2
t26: i32 = or disjoint t21, Constant:i32<1>
t24: v4i32 = insert_vector_elt t22, t6, t26
t25: v2i64 = bitcast t24
t16: ch,glue = CopyToReg t0, Register:v2i64 $v2, t25
t17: ch = PPCISD::RET_GLUE t16, Register:v2i64 $v2, t16:1
ISEL: Starting selection on root node: t26: i32 = or disjoint t21, Constant:i32<1>
Creating constant: t33: i32 = TargetConstant<31>
Creating new machine node: t34: i32 = RLWIMI t21, Constant:i32<1>, TargetConstant:i32<0>, TargetConstant:i32<31>, TargetConstant:i32<31>
It's strange that or X, 1
was selected into RLWIMI X, 1, 0, 31, 31
.
@llvm/issue-subscribers-backend-powerpc
Author: Chen Zheng (chenzheng1030)
we do it in more generically.
slwi 5, 6, n
li 3, Val
rlwimi 3, 5, 0, 0, K (K=31-n...31)
if 2^(31-n) >val
we can convert to
addi 3, 5, Val
or
ori 3, 5, Val
I agree. And a more generic pattern is we don't need to check the n
or slwi
instruction, we just need to check the trailing zero number of gpr5 in the rlwimi
instruction. If the trailing zero number is able to contain the Val
in li
, we can use addi/ori to combine li + rlwimi
.
See https://github.com/llvm/llvm-project/pull/86857/files#r1548822138
If we know the lowest bit of gpr5 is 0( slwi 5, 6, 1), PPC should be able to fold
to
Or