Open RKSimon opened 3 months ago
Hi!
This issue may be a good introductory issue for people new to working on LLVM. If you would like to work on this issue, your first steps are:
test/
create fine-grained testing targets, so you can e.g. use make check-clang-ast
to only run Clang's AST tests.git clang-format HEAD~1
to format your changes.If you have any further questions about this issue, don't hesitate to ask via a comment in the thread below.
@llvm/issue-subscribers-good-first-issue
Author: Simon Pilgrim (RKSimon)
@llvm/issue-subscribers-backend-aarch64
Author: Simon Pilgrim (RKSimon)
Soo, just to clarify what is expected (in more granular terms)
Soo, just to clarify what is expected (in more granular terms)
1. Add SimplifyDemandedVectorEltsForTargetNode() for AArch64 in: Target/AArch64/AArch64ISelLowering.cpp and make a case for handling AArch64ISD::DUP && AArch64ISD::DUPLANE nodes
Actually, I think we just need to handle AArch64ISD::DUPLANE - if the incoming DemandedElts mask is JUST the lane index bit then we can return the DUPLANE source directly (I think - not sure is the source can be a different vector width?). Otherwise we need to call a new DemandedElts mask on the source vector which is just the lane index.
2. In performDUPCombine, add a case to match AArch64ISD::DUPLANE, then use the call to the newly implemented SimplifyDemandedVectorEltsForTargetNode. Is this right?
We never call SimplifyDemandedVectorEltsForTargetNode directly - it will be a call to TLI.SimplifyDemandedVectorElts
@RKSimon, I'd be happy to take this on if no one else is currently working on it.
@SahilPatidar I'd recommend first completing the issues that are already assigned (unless you already have a patch?)
Hi @RKSimon, can I take this issue?
Thanks - I'm currently working on this. Apologies for the delay.
Noticed on #86284 - aarch64 is missing SimplifyDemandedVectorElts handling to/from AArch64ISD::DUPLANE nodes