Closed krzysz00 closed 5 months ago
@llvm/issue-subscribers-backend-amdgpu
Author: Krzysztof Drewniak (krzysz00)
Just about anything that perturbs the IR will hide anything in register allocation, which is essentially random. You can get further by reducing MIR, which you can do with llvm-reduce
Closed as vague ticket that doesn't help anyone
Closed as vague ticket that doesn't help anyone
It's useful if it reproduces still. Also the trick with these is to reduce all the way to minimal -start-before/-stop-after MIR sample
The issue
LLC crashes as follows on an input attached below
A
git bisect
run isolated this crash to only happening after #74467 .While full reproduction information and variant inputs/settings that do or don't cause the crash to occur are provided below, I can report that the flag
-amdgpu-codegenprepare-disable-idiv-expansion=true
removes the failure.Reproduction files
All of these files are
opt -O3 -mtriple=amdgcn-amd-amdhsa
output.I apologize in advance for the lack of a smaller test case, as
bugpoint
didn't have much luck with this one.reproducer.ll.txt is the input that triggers the crash. It is a matrix multiplication implementation.
fewer-batches-passing.ll.txt is that same code but with a lower batch size specified. That is, the input IR was identical to the failing case, but the statically-known (and annotated as a
!range
) number of workgroups differed between these two files.In relevant part, the diff between those two files is
reproducer-barriers-removed.ll.txt is
reproducer.ll
with thecall void asm
statements removed. This variant also does not crash.Steps to reproduce
(The
-mattr
inputs are kept to mach the original source of the bug)This will crash as seen above.
However,
will not crash
Similarly, replacing
reproducer.ll
with either of the two variant files will not trigger the bug.(Finally, adding
-global-isel
will also avoid the crash)