Open Validark opened 2 months ago
Can you try https://github.com/llvm/llvm-project/pull/85066?
@dtcxzyw Looks like the transformation does not happen due to the AND with 63.
@dtcxzyw Looks like the transformation does not happen due to the AND with 63.
This is a codegen patch. And it hasn't been merged into main. You should apply this patch and run llc on your local machine.
does not happen due to the AND with 63.
is_zero_poison
should be marked as true (based on the dominating condition), then the and inst will be eliminated.
BTW, opt -O3
already folds this pattern as you expected. Doesn't zig compiler use the default optimization pipeline?
godbolt: https://zig.godbolt.org/z/7qoEjox3K
Originally posted by @RKSimon in https://github.com/llvm/llvm-project/issues/90000#issuecomment-2081442262
This code:
Gives me this emit for the risc-v sifive u74:
Exactly what we want.
Now, let's "upgrade" to the sifive x280:
Oops! Same problem occurs on x86 Zen 3:
And on aarch64 apple_latest:
Godbolt link
Related: https://github.com/llvm/llvm-project/issues/84763 https://github.com/llvm/llvm-project/issues/90000