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riscv: Added Zvinsert instructions #92262

Open abel-bernabeu opened 5 months ago

abel-bernabeu commented 5 months ago

The Zvinsert optional extension for Zv enables data movement between integer scalar registers and arbitrary elements of a vector register.

The implementers of this extension provide a convenient alternative to spilling scalar registers to memory, using vector registers as alternative storage for saving and restoring scalar registers.

More patches exploiting the new possibilities in LLVM should come soon.

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asb commented 5 months ago

The Zvinsert optional extension for Zv enables data movement between integer scalar registers and arbitrary elements of a vector register.

Hi Abel - where might I find the draft spec for this? I couldn't find it on google or GitHub.

abel-bernabeu commented 5 months ago

Alex,

This extension is not yet ratified. The discussion of Zvinsert is ongoing on the RISC-V Vector SIG mailing list. The current version is 0.94 and some minor changes are still expected, although the encoding seems stable. Find the latest draft from today attached.

I am making this LLVM patch available as a draft pull request for several reasons:

Zvinsert Vector Extension.pdf

abel-bernabeu commented 5 months ago

GitHub should notify you again when the pull request goes from "draft" status to "ready for review".

github-actions[bot] commented 5 months ago

:warning: C/C++ code formatter, clang-format found issues in your code. :warning:

You can test this locally with the following command: ``````````bash git-clang-format --diff 398162ddbcf741c49e86bef2ef4aaa3fd0213916 6c9ba34b013424e705a61e5a5500edef2903bdc8 -- llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp ``````````
View the diff from clang-format here. ``````````diff diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index e2c0681933..e6db576a19 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -553,8 +553,9 @@ DecodeStatus RISCVDisassembler::getInstruction32(MCInst &MI, uint64_t &Size, "RV32Zacas table (Compare-And-Swap and rv32)"); TRY_TO_DECODE_FEATURE(RISCV::FeatureStdExtZfinx, DecoderTableRVZfinx32, "RVZfinx table (Float in Integer)"); - TRY_TO_DECODE_FEATURE(RISCV::FeatureStdExtZvinsert, DecoderTableRVZvinsert32, - "RVZvinsert table (Moves between Scalars and Vector Elements)"); + TRY_TO_DECODE_FEATURE( + RISCV::FeatureStdExtZvinsert, DecoderTableRVZvinsert32, + "RVZvinsert table (Moves between Scalars and Vector Elements)"); TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXVentanaCondOps, DecoderTableXVentana32, "Ventana custom opcode table"); TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadBa, DecoderTableXTHeadBa32, ``````````