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[aarch64] Spurious optimization of `cmtst+bif+bif` to `shl+cmlt+bif+shl+cmlt+bif` #92269
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Validark opened 3 months ago
https://zig.godbolt.org/z/Mf86PTv48
Compiled on aarch64:
If you switch the
bsl
<-->bsl2
names, you get:arm32 has the same problem with the
and/andn
definition ofbsl
. TheXOR
definition would probably have the same problem once https://github.com/llvm/llvm-project/issues/92267 is resolved.