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The LLVM Project is a collection of modular and reusable compiler and toolchain technologies.

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[ ] Implement WaveIsFirstLane clang builtin,
[ ] Link WaveIsFirstLane clang builtin with hlsl_intrinsics.h
[ ] Add sema checks for WaveIsFirstLane to CheckHLSLBuiltinFunctionCall in SemaChecking.cpp
[ ] Add codegen for WaveIsFirstLane to EmitHLSLBuiltinExpr in CGBuiltin.cpp
[ ] Add codegen tests to clang/test/CodeGenHLSL/builtins/WaveIsFirstLane.hlsl
[ ] Add sema tests to clang/test/SemaHLSL/BuiltIns/WaveIsFirstLane-errors.hlsl
[ ] Create the int_dx_WaveIsFirstLane intrinsic in IntrinsicsDirectX.td
[ ] Create the DXILOpMapping of int_dx_WaveIsFirstLane to 110 in DXIL.td
[ ] Create the WaveIsFirstLane.ll and WaveIsFirstLane_errors.ll tests in llvm/test/CodeGen/DirectX/
[ ] Create the int_spv_WaveIsFirstLane intrinsic in IntrinsicsSPIRV.td
[ ] In SPIRVInstructionSelector.cpp create the WaveIsFirstLane lowering and map it to int_spv_WaveIsFirstLane in SPIRVInstructionSelector::selectIntrinsic.
[ ] Create SPIR-V backend test case in llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveIsFirstLane.ll

DirectX

DXIL Opcode	DXIL OpName	Shader Model	Shader Stages
110	WaveIsFirstLane	6.0	('library', 'compute', 'amplification', 'mesh', 'pixel', 'vertex', 'hull', 'domain', 'geometry', 'raygeneration', 'intersection', 'anyhit', 'closesthit', 'miss', 'callable', 'node')

SPIR-V

OpGroupNonUniformElect:

Description:

Result is true only in the active invocation with the lowest id in the group, otherwise result is false.

Result Type must be a Boolean type.

Execution is a Scope that identifies the group of invocations affected by this command. It must be Subgroup.

Capability:
GroupNonUniform

Missing before version 1.3.

Word Count	Opcode	Results	Operands
4	333	<id> Result Type	Result <id>	Scope <id> Execution

Test Case(s)

Example 1

//dxc WaveIsFirstLane_test.hlsl -T lib_6_8 -enable-16bit-types -O0

export bool fn() {
    return WaveIsFirstLane();
}

HLSL:

Returns true only for the active lane in the current wave with the smallest index.

Syntax

bool WaveIsFirstLane(void);

Parameters

This function has no parameters.

Return value

True only for the active lane in the current wave with the smallest index.

Remarks

This function can be used to identify operations that are to be executed only once per wave.

This function is supported from shader model 6.0 in all shader stages.

Examples

 if ( WaveIsFirstLane() )
{
    . . . // once per-wave code
}

- [ ] Implement `WaveIsFirstLane` clang builtin, - [ ] Link `WaveIsFirstLane` clang builtin with `hlsl_intrinsics.h` - [ ] Add sema checks for `WaveIsFirstLane` to `CheckHLSLBuiltinFunctionCall` in `SemaChecking.cpp` - [ ] Add codegen for `WaveIsFirstLane` to `EmitHLSLBuiltinExpr` in `CGBuiltin.cpp` - [ ] Add codegen tests to `clang/test/CodeGenHLSL/builtins/WaveIsFirstLane.hlsl` - [ ] Add sema tests to `clang/test/SemaHLSL/BuiltIns/WaveIsFirstLane-errors.hlsl` - [ ] Create the `int_dx_WaveIsFirstLane` intrinsic in `IntrinsicsDirectX.td` - [ ] Create the `DXILOpMapping` of `int_dx_WaveIsFirstLane` to `110` in `DXIL.td` - [ ] Create the `WaveIsFirstLane.ll` and `WaveIsFirstLane_errors.ll` tests in `llvm/test/CodeGen/DirectX/` - [ ] Create the `int_spv_WaveIsFirstLane` intrinsic in `IntrinsicsSPIRV.td` - [ ] In SPIRVInstructionSelector.cpp create the `WaveIsFirstLane` lowering and map it to `int_spv_WaveIsFirstLane` in `SPIRVInstructionSelector::selectIntrinsic`. - [ ] Create SPIR-V backend test case in `llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveIsFirstLane.ll` ## DirectX | DXIL Opcode | DXIL OpName | Shader Model | Shader Stages | | ----------- | ----------- | ------------ | ------------- | | 110 | WaveIsFirstLane | 6.0 | ('library', 'compute', 'amplification', 'mesh', 'pixel', 'vertex', 'hull', 'domain', 'geometry', 'raygeneration', 'intersection', 'anyhit', 'closesthit', 'miss', 'callable', 'node') | ## SPIR-V # [OpGroupNonUniformElect](https://registry.khronos.org/SPIR-V/specs/unified1/SPIRV.html#OpGroupNonUniformElect): ## Description: Result is **true** only in the active [invocation](https://registry.khronos.org/SPIR-V/specs/unified1/SPIRV.html#Invocation) with the lowest id in the [group](https://registry.khronos.org/SPIR-V/specs/unified1/SPIRV.html#Group), otherwise result is false. *Result Type* must be a [*Boolean type*](https://registry.khronos.org/SPIR-V/specs/unified1/SPIRV.html#Boolean). *Execution* is a [*Scope*](https://registry.khronos.org/SPIR-V/specs/unified1/SPIRV.html#Scope_-id-) that identifies the group of invocations affected by this command. It must be **Subgroup**. [Capability](https://registry.khronos.org/SPIR-V/specs/unified1/SPIRV.html#Capability): **GroupNonUniform** [Missing before](https://registry.khronos.org/SPIR-V/specs/unified1/SPIRV.html#Unified) **version 1.3**. <table> <colgroup> <col style="width: 20%" /> <col style="width: 20%" /> <col style="width: 20%" /> <col style="width: 20%" /> <col style="width: 20%" /> </colgroup> <thead> <tr> <th>Word Count</th> <th>Opcode</th> <th>Results</th> <th>Operands</th> <th></th> </tr> </thead> <tbody> <tr> <td class="tableblock halign-left valign-top"><p>4</p></td> <td class="tableblock halign-left valign-top"><p>333</p></td> <td class="tableblock halign-left valign-top"><p><em><id></em><br /> <em>Result Type</em></p></td> <td class="tableblock halign-left valign-top"><p><a href="#ResultId"><em>Result <id></em></a></p></td> <td class="tableblock halign-left valign-top"><p><a href="#Scope_-id-"><em>Scope <id></em></a><br /> <em>Execution</em></p></td> </tr> </tbody> </table> ## Test Case(s) ### Example 1 ```hlsl //dxc WaveIsFirstLane_test.hlsl -T lib_6_8 -enable-16bit-types -O0 export bool fn() { return WaveIsFirstLane(); } ``` ## HLSL: Returns true only for the active lane in the current wave with the smallest index. ## Syntax ``` syntax bool WaveIsFirstLane(void); ``` ## Parameters This function has no parameters. ## Return value True only for the active lane in the current wave with the smallest index. ## Remarks This function can be used to identify operations that are to be executed only once per wave. This function is supported from shader model 6.0 in all shader stages. ## Examples ``` syntax if ( WaveIsFirstLane() ) { . . . // once per-wave code } ``` ## See also <dl> <dt> [Overview of Shader Model 6](https://github.com/MicrosoftDocs/win32/blob/docs/desktop-src//direct3dhlsl/hlsl-shader-model-6-0-features-for-direct3d-12.md) </dt> <dt> [Shader Model 6](https://github.com/MicrosoftDocs/win32/blob/docs/desktop-src//direct3dhlsl/shader-model-6-0.md) </dt> </dl>