lneuhaus
commented
5 years ago There is currently no text document with the register addresses. You either have to go through the verilog code and figure out how the bus address input is disassebled to route signals to/from the corresponding pyrpl module, or check the python code. For a beginner it is probably easier to figure this out from the verilog source code. Start in red_pitaya_top.v and look for the bus address register, and try to understand what is done to it. This should take maybe 30 minutes, but you will have understood how the bus works after that.
Hi,
I am a starter of Redpitaya Board. Currently I am trying to use the code in https://github.com/lneuhaus/RedPitaya/tree/master/fpga/rtl. However, I cannot find the definition of the register allocation for each modules. For example, in STEMlab document, we can see that the register for HK is 0x40000000 to 0x400FFFFF and the register for Scope is 0x40100000 to 0x401FFFFF. Could you please give me a hint about where those definitions are in the verilog modules?
Thank you very much
Chen Wu