Zhou-Yilong
commented
1 year ago By the way ,my flow is:
LSOracle flow: yosys: read_verilog test.v yosys: synth -top topmodule -flatten yosys: lsoracle (oracle --out oracled.v) abc: read_verilog oracled.v abc: read_lib tech.lib abc: strash abc: map abc: topo abc: sitme (I use this command to do STA and prints area & delay )
abc resyn2rs flow: yosys: read_verilog test.v yosys: synth -top topmodule -flatten yosys: abc -c 'resyn2rs; write_verilog abced.v' abc: read_verilog abced.v abc: read_lib tech.lib abc: strash abc: map abc: topo abc: sitme
The flow is same except optimizaion.
Hi! I have tested the circuit, as well as EPFL combinational circuits, you mentioned in your paper and LSOracle2.0 with LSOracle and abc resyn2rs script, but the result shows that abc resyn2rs script performs better in most cases. I'm wondering there may be some mistakes in my test flow which leads to the problem above. May you guys give a detailed guide on how to do a correct test? Thanks inadvance sincerely!