tangxifan
commented
1 year ago Changes on user interface
Users can select if a programmable network is needed for each global signal, by adding XML description to the OpenFPGA architecture. New XML syntax will be introduced to the Physical Tile Annotation
<tile_annotations>
<global_port name="<string>" is_clock="<bool>" is_reset="<bool>" is_set="<bool>" default_val="<int>">
<network type="none|htree|fishbone" entry_x="<int>" entry_y="<int>" mux_circuit_model="<string>"/>
<tile name="<string>" port="<string>" x="<int>" y="<int>"/>
...
</global_port>
</tile_annotations>The network type will be none by default, which means the global port will be connected directly to each sink (just as current OpenFPGA's behavior)
If specified as H-tree or Fishbone, an entry point (x, y) is required.
mux_circuit_model is to select the circuit model of routing multiplexers to be considered, when building programmable switches in switch blocks.
ganeshgore
Is your feature request related to a problem? Please describe. Global signals, such as
clock,resetandset, span a complete or a considerable portion of FPGA fabrics. From a physical design perspective, the global signals require a dedicated network to route a source to all the sinks. Common practice to implement the networks includes:Each implementation carries different consideration on latency and skews, which are highly dependent on the product requirements.
Currently, in the fabric netlists that are auto-generated by OpenFPGA do not include any network for global signals. It assumes that physical designers should implement the networks through tools, such as Synopsys ICC2 or Cadence Innovus. However, in recent researches, we see that Clock Tree Synthesis in modern ASIC tools cannot efficiently implement these networks in a reasonable runtime [1]. Researchers also show that adding pre-routed networks to fabric netlists is a practical solution, with which layout of a 100k-LUT FPGA can be accomplished in 24 hours.
Given the importance of the networks, it is necessary to support the dedicated networks in OpenFPGA's fabric generator. It avoids manual and massive netlist changes before physical design, which
[1] Ganesh Gore, Xifan Tang, and Pierre-Emmanuel Gaillardon. 2021. A Scalable and Robust Hierarchical Floorplanning to Enable 24-hour Prototyping for 100k-LUT FPGAs. In Proceedings of the 2021 International Symposium on Physical Design (ISPD '21). Association for Computing Machinery, New York, NY, USA, 135–142. https://doi.org/10.1145/3439706.3447047
Describe the solution you'd like
Driven by the needs on modern FPGA architectures, the global signal may need not only a dedicated but also programmable network. The networks can be either H-tree or Fishbone. Programmable switches (routing multiplexers) may exist in the network, allowing chip designers to turn off part of the networks for the sake of power saving. The following figure illustrates how the programmable switches and dedicated routing tracks will be appended to routing blocks, such as Switch Block (SB), X-directional Connection Block (CBX) and Y-directional Connection Block (CBY)
Note that the routing multiplexers can be configured by configuration memory, e.g., SRAM. OpenFPGA can generate associated bitstream to configure each routing multiplexer. Using a programmable network, sink of each programmable block can be reached, by downloading a proper bitstream.